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IRS2334SPbF/MPbF
with a low voltage, which would result in power switches conducting current while with a high channel impedance,
which would produce very high conduction losses possibly leading to power device failure.
V CC
(or B )
V CCU +
V CCU -
(or BSU + )
(or BSU - )
Time
UVLO Protection
(Gate Driver Outputs Disabled)
Norma
Operation
Norma
Operation
Figure 8: UVLO protection
Truth Table: Under-Voltage lockout
Table 2 provides the truth table for the IRS2334 HVIC.
The 1 st line shows that for V CC below the UVLO threshold both the gate driver outputs LO and HO are disabled.
After V CC returns above V CCUV , the gate driver outputs return functional.
The 2 nd line shows that for V BS below the UVLO threshold, the gate driver output HO is disabled. After V BS returns
above V BSUV , HO remains low until a new rising transition of HIN is received.
The last line shows the normal operation of the HVIC.
VCC
VBS
outputs
LO
HO
UVLO V CC
<V CCUV
0
0
UVLO V BS
Normal operation
15 V
15 V
<V BSUV
15 V
LIN
LIN
0
HIN
Table 2: UVLO truth table
Advanced Input Filter
The IRS2334 HVIC provides an advanced input filter that improves the input/output pulse symmetry of the signals
processed by the HVIC. This input filter is inserted at the HIN and LIN input pins. The working principle of the
filter is shown in Figures 9 and 10.
Figure 9 shows a typical input filter and the asymmetry it produces on its output signal. The upper waveforms of
Example 1 show an input signal with a pulse duration mush longer than the filtering time t FILIN ; the resulting output
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